Fault Ride-Through (FRT) in BESS Inverters

1. Executive Summary & Grid Problem Statement

As variable renewable energy generation approaches 30% to 50% instantaneous penetration on regional transmission grids across India, the structural stability of the National Grid has become deeply reliant on the dynamic capabilities of inverter-based resources (IBRs). In earlier stages of renewable deployment, grid interconnection standards permitted solar and wind inverters to trip offline during severe transmission line faults to protect internal power electronics. Today, however, with individual pooling substations injecting hundreds of megawatts of renewable power, the simultaneous tripping of large-scale inverter plants during a transient transmission fault would cause catastrophic cascading voltage collapse and widespread grid blackouts.

Consequently, the Central Electricity Authority (CEA) enacted the landmark Technical Standards for Connectivity to the Grid (Amendment 2024), establishing mandatory, uncompromising Fault Ride-Through (FRT) standards. Utility-scale Battery Energy Storage Systems (BESS) connected at 33kV, 132kV, 220kV, or 400kV are not merely required to remain physically connected to the grid during severe symmetrical and asymmetrical voltage disturbances; they are legally mandated to act as active stabilizing assets. They must inject high-speed dynamic reactive current ($I_q$) during voltage sags (Low-Voltage Ride-Through, LVRT) and absorb reactive current during transient overvoltages (High-Voltage Ride-Through, HVRT).

Meeting these statutory mandates requires sophisticated Power Conversion System (PCS) engineering. Inverter control architectures are undergoing a fundamental paradigm shift from legacy Grid-Following (GFL) phase-locked loop (PLL) topologies to advanced Grid-Forming (GFM) virtual synchronous machine (VSM) algorithms capable of operating in ultra-weak grids with low Short-Circuit Ratios (SCR < 1.5). This technical whitepaper analyzes FRT electro-physical dynamics, evaluates LVRT/HVRT voltage envelopes, details high-speed reactive current injection sizing, and establishes CEA grid code compliance testing for utility BESS in India.

2. Core Physics, Electrochemistry & Architectural Design

Fault Ride-Through is the electro-mechanical capability of an inverter-based system to maintain stable synchronization and continuous power delivery through transient grid voltage anomalies without tripping offline on overcurrent, DC-link overvoltage, or loss of synchronism.

When a three-phase short-circuit fault occurs on an adjacent 220kV or 400kV transmission line, the voltage at the Point of Common Coupling (PCC) collapses instantaneously—often plunging to near 0.0V (a solid zero-voltage fault). The dynamic response of a utility BESS inverter is governed by the statutory LVRT and HVRT curves defined in CEA Technical Standards 2024:

During a deep voltage collapse ($V o 0$), the physical ability of the inverter to export active power ($P = 3 \cdot V \cdot I$) drops to near zero. However, power from the 1500V DC battery containers continues flowing into the inverter's DC-link capacitors. Unless the inverter controller acts within microseconds, the mismatch between input DC power and exported AC power rapidly charges the DC-link capacitor bank, triggering destructive DC overvoltage ($V_{dc} > 1550 ext{V}$) that destroys IGBT or SiC semiconductor switches.

3. Engineering Sizing, Thermal Gradients & Component Specifications

Engineering a BESS Power Conversion System to survive deep FRT events and inject high-speed reactive support requires precision coordination between internal DC-chopper protection, semiconductor thermal margins, and control loop vector physics.

1. Fast Active Current De-Rating & Dynamic Reactive Current Prioritization: When terminal voltage drops below 0.85 p.u., the PCS firmware immediately transitions from active power priority to reactive power priority. Within 20 milliseconds, the inverter injects reactive current ($I_q$) governed by the statutory K-factor equation ($\Delta I_q = K \cdot \Delta V \cdot I_n$, where $K = 2.0$). At a 50% voltage sag ($\Delta V = 0.5$), the inverter injects 100% of its rated current as pure reactive current ($I_q = 1.0 I_n$) to support grid voltage recovery.

2. DC-Bus Overvoltage Protection (Brake Chopper Architecture): To absorb excess DC energy when active power export is blocked during a fault, utility PCS units incorporate dynamic braking choppers. High-speed IGBT switches shunt surplus DC power across heavy-duty ceramic braking resistors within 50 microseconds, preventing DC-link overvoltage while the BMS and battery DC contactors are commanded to ramp down current.

3. Transition to Grid-Forming (GFM) Control: In weak grid interconnections characterized by low Short-Circuit Ratios ($SCR < 1.5$) and high X/R ratios typical of remote renewable zones in Rajasthan and Ladakh, conventional Grid-Following (GFL) inverters fail. GFL inverters rely on Phase-Locked Loops (PLL) to track grid voltage phase angles; during a zero-voltage fault, the voltage vector vanishes, causing the PLL to lose synchronization and oscillate uncontrollably.

Grid-Forming (GFM) control eliminates the PLL entirely. Using Virtual Synchronous Machine (VSM) algorithms, the GFM inverter operates as an ideal internal voltage source behind a transient reactance, synthesizing its own internal voltage phasor ($\mathbf{E} ngle heta$). During a fault, the GFM inverter naturally and instantaneously injects fault current governed by the physical network impedance ($\mathbf{I} = (\mathbf{E} - \mathbf{V}_{grid}) / \mathbf{Z}$), delivering true physical inertia to the grid without measurement delay.

4. Statutory CEA Standards & Balance-of-Plant (BoP) Integration

Compliance with Fault Ride-Through standards is legally binding under Central Electricity Authority (Technical Standards for Connectivity to the Grid) Regulations, 2024 and Central Electricity Regulatory Commission (Indian Electricity Grid Code) Regulations.

Key statutory compliance benchmarks:

• Post-Fault Active Power Recovery Rate: CEA regulations mandate that upon fault clearance (when grid voltage recovers above 0.85 p.u.), the BESS inverter must restore active power export to at least 90% of its pre-fault value at a minimum ramp rate of 20% of rated capacity per second (full recovery in less than 5.0 seconds). Prolonged active power recovery is penalized as non-compliant.
• Negative-Sequence Current Injection under Asymmetrical Faults: In the real world, over 90% of grid faults are asymmetrical (single line-to-ground or line-to-line faults). Inverters must independently regulate positive-sequence and negative-sequence currents, injecting negative-sequence reactive current to suppress unbalanced voltage phase distortions.
• Mandatory Type-Testing and Simulation Dossier: Prior to grid synchronization, the project developer must submit certified type-test reports from accredited laboratories (such as CPRI or international equivalents) proving LVRT/HVRT compliance on physical full-scale PCS skids, accompanied by validated PSCAD / MATLAB Simulink electromagnetic transient (EMT) models submitted to the Central Transmission Utility (PowerGrid / CTU).

5. Failure Modes, Safety Protocols & Commissioning Checkpoints

Failing to engineer robust FRT controls results in severe hardware damage and grid synchronization failures during transmission disturbances:

Critical Pitfalls in FRT Implementation:

• PLL Instability in Weak Grids: Tuning phase-locked loops with excessively high bandwidth causes control instability and high-frequency harmonic tripping during asymmetric faults. PLL gains must be optimized through dynamic impedance scanning, or replaced with grid-forming control.
• IGBT Thermal Over-Stressing during Repeated Faults: Multi-shot auto-reclosure cycles on 220kV overhead lines subject inverters to repeated short-circuit current surges within seconds. Sizing models must ensure that PCS semiconductor junctions have sufficient thermal capacitance to withstand back-to-back LVRT events without exceeding $T_j = 150^\circ ext{C}$.
• DC-Link Capacitor Degradation: Repeated high-voltage transient spikes during HVRT events degrade metallized polypropylene film DC-link capacitors, accelerating electrolyte dry-out. Capacitors must be specified with a 20-year service life at 105°C and 1,800V DC surge withstand ratings.

Site commissioning mandates physical mobile test container testing (FRT mobile test trailer) applying calibrated voltage sags at the 33kV pooling substation, recording inverter response with high-speed transient fault recorders to verify that $I_q$ injection latency is strictly under 20 milliseconds.